The present invention relates to a method for fabricating a semiconductor device having an insulated gate, (hereinafter referred to as an insulated gate semiconductor device), and more particularly to a method for fabricating such a device as is suitable to provide a high current density.
The semiconductor device to which the present invention relates has such a structure as shown in FIG. 5. In this figure, 11 is an n.sup.+ -type or p.sup.+ -type semiconductor substrate; 12 is an n.sup.- -type layer formed on the semiconductor substrate 11 and having a higher resistivity than the semiconductor substrate 11; 13 are a plurality of p.sup.+ -type wells which extend into the n.sup.- -type layer 12 from the surface thereof on the side opposite to the side adjacent to the semiconductor substrate 11; 15 are n.sup.+ -type sources which extends into the p.sup.+ -well 13 from the surface thereof; 31 are gate electrodes each formed on the exposed portions of the n.sup.- -type layer 12 and p-type well 13 adjacent thereto through a gate oxide film 21; 22 are insulating films each formed so as to cover the gate electrode 31 and a part of the n.sup.+ -type source layer 15 adjacent thereto; 41 is a drain electrode kept in ohmic contact with the surface of the semiconductor substrate 11 on the side opposite to the side adjacent to the n.sup.- -type layer 12; and 42 is a source electrode kept in ohmic contact with the exposed portions of the n.sup.+ -source layers 15 and of the p-type wells 13 between the n.sup.+ -source layers and formed so as to extend over the insulating films 22.
The semiconductor device as shown is an unipolar device commonly called "MOSFET" in the case where the semiconductor substrate 11 is of n.sup.+ -type In operation, if, with the source electrode 42 applied with e.g. 0 V and the drain electrode 41 applied with a positive potential, a positive potential is applied to the gate electrode 31, an n-type inverted layer is produced in the p-type well layer 13 under the gate electrode 31 and electrons .crclbar. flow to the drain electrode 41 through the source electrode 42, the n.sup.+ -type source layer 15, the n-type inverted layer, the n.sup.- -type layer 12 and the n.sup.+ -type substrate. Thus, current flows from the drain electrode 41 to the source electrode 42, whereby the semiconductor device turns on. Then, if the potential which has been applied to the gate electrode 31 is removed, the p-type inverted layer disappears. Thus, the path of electrons .crclbar. is cut off whereby the semiconductor device turns off.
On the other hand, in the case where the semiconductor substrate 11 is of p.sup.+ -type, the semiconductor device as shown is a bi-polar device called a conductivity-modulated MOSFET and IGBT (insulated gate bipolar transistor). In operation, potentials are applied to the source electrode 42 and the drain electrode 41 in the same manner as the case where the semiconductor substrate 11 is p.sup.+ -type. Now, if a positive potential is applied to the gate electrode 31, electrons flow in the n.sup.- -type layer 12. Then, the electrons accelerate the injection of a large amount of holes from the p.sup.+ -type substrate, thereby producing a large amount of excess carriers in the n.sup.- -type layer 12. Thus, the n.sup.- -type layer 12 which has been of a higher resistivity exhibits a conductivity of lower resistivity. This is the reason why that semiconductor device is called "conductivity modulated MOSFET", in which the electrons serve as a base current and a pnp transistor consisting of the p.sup.+ -type substrate 11, the n.sup.- -type layer 12 and the p-type well layer 13 is operated. The injected holes flow into the source electrode 42 through the p-type well layer 13 under the n.sup.+ -type source layer 15. In order to turn off the conductivity modulated MOSFET, the potential applied to the gate electrode 31 is removed as in the case of the unipolar MOSFET. Then, the path of electrons .crclbar. is cut off so that the base current of the pnp transistor is not supplied. Thus, the holes are not injected whereby the current does not flow.
The semiconductor device having such a structure as described above has been proposed in U.S. Pat. No. 4,364,073, U.S. Pat. No. 4,587,713 and Solid State Electronics 28 No. 3 pp 389 to 297 (1985) "Temperature Behavior of Insulated Gate Transistor Characteristics" by B. J. Baliga, etc.
A process of fabricating such a semiconductor device as mentioned above will be explained with reference to FIGS. 6A to 6F. First, an n.sup.+ -type or p.sup. -type semiconductor substrate 11 is prepared and an n.sup.- -type layer 12 is formed on one surface thereof. A stack (insulated gate) of a gate oxide film 21 and a gate electrode 31 are selectively formed on the surface of the n.sup.- -type layer 12 on the side opposite to the side adjacent to the semiconductor substrate 11 (FIG. 6A). Using this stack as a mask, boron (B) is ion-implanted in the surface of the n.sup.- -type layer 12 where no mask is located thereon, and the substrate is heat-treated to form a p-type well layer 13 (FIG. 6B). A resist film 29 is formed on the p-type well layer 13 surface at the selected location thereof. Using, as a mask, this resist film and the stack of the gate oxide film 21 and the gate electrode 31, arsenic (As) or phosphorus (P) is ion-implanted in the p-type well layer 13 surface at the location where the mask is not present, (FIG. 6C). After the ion-implatation, the resist film 29 is removed and the substrate is heat-treated to form n.sup.+ -type source layers 15 (FIG. 6D). An insulating film 22 is formed on the stack consisting of the gate oxide film 21 and the gate electrode 31 and on the exposed portions of the p-type well layer 13 and the n.sup.+ -type source layer 15 (FIG. 6E). A portion of the insulating film 22 located on portions of the n.sup.+ -type source layers and a portion of the p-type well layer 13 exposed between the n.sup.+ -layer source layers 15 is selectively removed and a source electrode 42 is formed on the remaining insulating film 22 and on the portions of the n.sup.+ -type source layers 15 and the p-type well layer 13 exposed by removing the portion of the insulating film 22 (FIG. 6F).
The insulating gate semiconductor device fabricated by the process as mentioned above has a disadvantage that it can not provide a high current density. The current density of the semiconductor device having an insulated gate as shown in FIG. 5 can be enhanced by providing a larger percentage area occupied by the gate region B in a device unit and a smaller percentage area occupied by the remaining region A. However, in the case where the semiconductor device is fabricated by the process as shown in FIGS. 6A to 6F, the area of the region A can not be decreased for the following reason. Namely, if an alignment accuracy of photolithography is 3 .mu.m, size A.sub.1 of the insulating film 22 required to insulate the gate electrode 31 from the source electrode 42, size A.sub.2 required to surely bring the source electrode 42 and the n.sup.+ -type layers 15 into contact with each other, and size A.sub.3 required to separate the n.sup.+ -type layers 15 from each other and bring the p-type layer 13 and the source electrode 42 into contact with each other, which depends on the processing accuracy of the resist film 29, are required to be at least 3 .mu.m. Since these sizes must take some allowance considering the safety rates, the entire width (2A.sub.1 +2A.sub.2 +A.sub.3) of the region A reaches 20 to 30 .mu.m, which will occupy 50% of the device unit. Thus, the percentage of the gate region B can not be further increased, which makes it impossible to enhance the current density.
In the case of a conductivity modulated MOSFET using a p.sup.+ -type substrate, if the width (A.sub.1 +A.sub.2) of the n.sup.+ -type source layer 15 is too large, injected holes .sym. produce a voltage drop in the p-type well layer 13 due to the lateral resistance R in the p-type well layer 13 under the n.sup.+ -type layer 15, thereby forward biasing the n.sup.+ -type source layer 15 and the p-type well layer 13. Thus, an npn transistor consisting of the n.sup.+ -type source layer 15, the p-type well layer 13 and the n.sup.- -type layer 12 is started to operate, thus injecting electrons into the p-type well layer 13 from the n.sup.+ -type source layer 15. Accordingly, the semiconductor device operates as a pnpn thyristor which includes the pnp transistor consisting of the layers 11, 12 and 13 as mentioned above, and is eventually latched up. Once latched up, the semiconductor device can not be turned off even when the potential applied to the gate electrode 31 is removed, which makes it impossible to control the semiconductor device through the gate.
Such a problem also occurs in the unipolar MOSFET when it shifts from the turn-on state thereof to the turn-off state thereof.
In order to surely operate the insulated gate semiconductor device, the parasitic transistor effect as mentioned above is desired to be made as small as possible.